This application is based on and claims the benefit of priorities from prior Japanese Patent Applications No. 2001-69791, filed on Mar. 13, 2001, and No. 2001-331158, filed on Oct. 29, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to semiconductor devices with a polycrystalline silicon germanium film for use as gate electrodes, and also relates to a method of fabricating the same.
2. Description of Related Art
Recently, integrated circuit (IC) chips employing metal insulator semiconductor field effect transistors (MISFETs) are becoming thinner and thinner in gate dielectric films on the basis of scaling rules, resulting in usage of gate dielectric films with a thickness of 3 nanometers (nm) or less. With such thin gate dielectric film-based MISFETs, the capacitance of a silicon substrate and the capacitance of a gate electrode as equivalently series-coupled with respect to the capacitance of a gate dielectric film becomes more significant appreciably, which leads to unattainability of any gate capacitance increase otherwise expectable due to a decrease in gate dielectric film thickness.
A parasitic capacitance as induced due to depletion of a gate electrode made of polycrystalline silicon is determinable in value largely depending upon a concentration of active impurities residing within the polycrystalline silicon or xe2x80x9cpolysiliconxe2x80x9d: the less the active impurity concentration, the greater the parasitic capacitance value. Accordingly, it is desired that the active impurity concentration of a polysilicon gate electrode is as high as possible. However, the degree of activation of such impuritiesxe2x80x94say, impurity activation ratioxe2x80x94is simply determined by the solubility of impurities and thus must be limited in value. In particular, in the case of introduction of a p-type impurity into polysilicon, it is difficult to obtain any activated impurity concentration that is greater in value than possible with currently available ones.
With highly miniaturized or xe2x80x9cmicrofabricatedxe2x80x9d IC elements, the presence of a need to form shallow source and drain diffusion layers results in thermal processing for impurity activation also decreasing both in temperature and in length of time period required. This also limits the impurity activation ratio of polysilicon gate electrodes. And, if the impurity activation ratio stays low then the resulting parasitic capacitance increases while at the same time disabling achievement of electrical resistivity reduction of gate electrodes. This in turn leads to an inability to obtain any required high-speed performance.
One approach proposed today to avoiding this problem is to form gate electrodes by use of a polycrystalline silicon germanium (SiGe) film that is inherently higher in impurity solubility than polysilicon. Unfortunately, recent study and research results have revealed that this approach does not come without accompanying a penalty which follows. In cases where an n-type impurity such as phosphorus (P) or the like is introduced into polycrystalline SiGe material, the resultant activation ratio becomes lower than possible with polysilicon if the Ge concentration gets higher. This is suggested from some papers; for example, 1) T. J. King et al., ED-41, p. 228 (1994) and 2) W. C. Lee et al., EDL-19, p. 247 (1998).
See FIGS. 35 and 36. These graphs indicate experimental data as presented in the above-identified two documents (xe2x80x9cD1xe2x80x9d and xe2x80x9cD2xe2x80x9d). More specifically, FIG. 35 is a graph demonstrating plots of activation ratios of boron (B) and phosphorus (P) as a function of germanium (Ge) concentration in polycrystalline SiGe whereas FIG. 36 shows plots of activated impurity concentration of B and P versus Ge concentration. Note here that these value-change curves are under the condition that thermal processing for activation was done at a temperature of 900xc2x0 C. for forty minutes. It is very likely that the use of arsenide (As) yields in similar results to P. In this way, whereas p-type impurities increase in impurity activation ratio with an increase in Ge concentration within a limited range of up to approximately 40 atomic percent (atm %) of Ge concentration, n-type impurities are such that the activation ratio thereof rapidly drops down when Ge concentration goes beyond about 20 to 30 atm %. In view of this, D2 teaches that it should be required to set the Ge concentration at 20 atm % or more or less when gate electrodes of a complementary metal oxide semiconductor (CMOS) circuit are formed of a polycrystalline SiGe film.
On the contrary, in mixed or xe2x80x9chybridxe2x80x9d LSI chips with logic circuits and dynamic random access memories (DRAMs) or analog circuits integrated or xe2x80x9cembeddedxe2x80x9d together, potentially different internal power supply voltages are ordinarily used in units of circuit regions in most cases. More specifically a plurality of types of CMOS circuits operable with multiple supply voltages are formed together on the same silicon substrate. Obviously such supply voltage-different CMOS circuits are required to employ gate dielectric films that are different in film thickness from one another. Generally the film thickness of a gate oxide film is designed so that an electrical field being applied thereto falls within a specified range of from 4 to 5 MV/cm.
A typical process of forming a plurality of kinds of gate oxide films is as follows. After having formed a thick gate oxide film on the entire surface area of a silicon substrate, this film is partially etched away to thereby form thin gate oxide films. However, forming such multiple different gate oxide films at different on-chip locations does call for execution of both resist coating process and peel-off process on or above the gate oxide films, which would result in a decrease in long-term reliability. Additionally a thicker gate oxide film must be formed through two extra oxidation steps; thus, the film thickness controllability decreases causing the resultant film to undesirably increase or decrease in thickness.
As apparent from the foregoing, the approach to fabricating a CMOS circuit having more than one gate electrode formed of a polycrystalline SiGe film suffers from a problem as to an inability to take full advantages or merits as derived from the use of a polycrystalline SiGe film, due to a difference in activation ratio between p-type and n-type impurities.
Another problem faced with LSI chips with built-in circuits operable with a plurality of different power supply voltages is that formation of gate dielectric films of different film thickness values can result in decreases in reliability and in film thickness controllability.
In accordance with one aspect of this invention, there is provided a semiconductor device which comprises a semiconductor substrate, a first transistor having a first gate electrode overlying the semiconductor substrate and being formed of a polycrystalline silicon germanium film, and a second transistor having a second gate electrode overlying the semiconductor substrate and being formed of a polycrystalline silicon germanium film different in germanium concentration from the first gate electrode.
In accordance with another aspect of the invention, there is provided a method of fabricating a semiconductor device, which comprises: depositing a polycrystalline silicon germanium film above a semiconductor substrate with a gate dielectric film interposed therebetween; patterning the polycrystalline silicon germanium film to form gate electrodes in first and second circuit regions, respectively; selectively oxidizing prior to or after execution of the patterning of the gate electrodes a surface of the polycrystalline silicon germanium film in the second circuit region to thereby increase its germanium concentration; and forming source and drain diffusion layers that are self-aligned with the gate electrodes.